Concurrent subsystem diagnostics and i/o controller

ABSTRACT

Diagnostics in a peripheral subsystem for a data processing system are performed on a concurrent basis with other programs in the data processing system. The peripheral subsystem has capabilities of generating indications for the data processing system representative of operational conditions that could be encountered; the data processing system is programmed to respond to said indications for diagnosing the operational capabilities of the connected peripheral subsystem. Included in the diagnostics are interface checking between the subsystem and the rest of the data processing system, device status, capability of stacking status, capability of handling nonstackable status, verifying enable/disable operation, and checking device busy status and the like.

[ Apr. 23, 1974 Primary ExaminerPaul J. Henon Assistant ExaminerMelvin B. Chapnick Attorney, Agent, or Firm-Herbert F. Somermeyer [57] ABSTRACT Diagnostics in a peripheral subsystem for a data processing system are performed on a concurrent basis with other programs in the data processing system. The peripheral subsystem has capabilities of generat- CONCURRENT SUBSYSTEM DIAGNOSTICS AND 1/0 CONTROLLER Inventor: Gene H. Edstrom, Longmont, Colo.

International Business Machines Corporation, Armonk, NY.

Filed: Aug. 5, 1971 Appl. No.: 169,193

United States Patent Edstrom {73] Assignee:

6 Drawing Figures Included in the diagnostics are interface checking between the subsystem and the rest of the ing indications for the data processing system representative of operational conditions that could be encountered; the data processing system is programmed to respond to said indications for diagnosing the operational capabilities of the connected peripheral subdata processing system, device status, capability of stacking status, capability of handling nonstackable status, verifying enable/disable operation, and checking device busy status and the like.

1 Claim,

OITROLLER BtRCUITS '64 m l 5 W. S n5 G H n|u mp m A 5W3 JS SSSS W A s 5 22 2 2 0 77 .77nn W 7 l a s 11 tlzllltl 0 .S l u ww wwww V M2 44H4444 it 3303333 h G mmu mmm u 2 H- n S 7 M T m m m A .//I H n H m n n H u.. H s i mm mmm .m d m H m mam m u H m mmmm s m H "t T m E u au. e on H n mri u nmn s u U k d U r l l l 1 l l l l l l l l l I I I I I I 5 1 4 l l l l l 4 l l l l l l l l l l l i i l i m w w mra t "H" T a non Hu .mSHHLHEZK E u c D n M E700 22 e T6777777 S l999w999 O 93766 4 d M 789583 .UIF 4409377 J 3495839 n .l. 40 3835 2 8 6 555 5 [l- 3333333 PATENTEU APR 23 m4 SHEET 1 (IF 5 i i SET DIAGNUSE ADEVWE B.CU (HMS CMDS CHAIN SUBSYSTEM FIG.1

101 CU FQRCES INDICATIONS CHAIN STATUS CHECK FORCED INDICATIONS AND (IND RESPONSES 14 BREAK FIG. 2

CPU

PERIPHERAL SUBSYSTEM 9015mm APR 23 100: .606, 878

SREU [1F 92 00s I 0 01 REGISTER A REGISTER I 1/ I/I JL; (M0 21 1 9a 2 X 0 1 5 05 INSTRUCTION BM 05 050005 EXCHANGE A HUS 050051500 111/ ..L REGISTER $1 1] HUS LSR 2 \86 F. 7 l [I], l Ill Ill/[Ill] 1/ I f Y m 10 87 14,15 Ill/I111 l/ i] A w Q A4 68 6Y-|NSTRUCT|0N m; REGSTER 69 CH BRANCH umnowsm zm ,[HUS 1 ,1 76 i %:T 8888A A I, 4 N R05 ADDRESS T; 5 00mm 1 CHECK 5 MEMORY cmcun 4 I I w 77 "-40,40A 66 HI W A J \msmucnou 5 A O m 1]! I III III/II II [III/III II [III III 050mm 00) 99A 40 1 000 l ={CL0CK|- m8 TRAP s0 ADDRESS I A k REGISTER mm ADDRBO I smus REGISTER 1 A H! 100mm CONTROHOTHER MPU) L0 0|r0 smn CONCURRENT SUBSYSTEM DIAGNOSTICS AND CONTROLLER DOCUMENTS INCORPORATED BY REFERENCE 1. IBM SYSTEMS JOURNAL, The Structure of System/360", Parts I and II, Vol. 3, No. 2, 1964, Pages 119 and 142, respectively by G. A. Blaauw and F. P. Brooks, .lr., and W. Y. Stevens.

2. IBM System/360 Engineering." by P. Fagg et al, PROCEEDINGS-FALL JOINT COMPUTER CON- FERENCE, 1964, Pages 205-231.

3. US. Pat. No. 3,214,739 (a two-channel switch or multiple interface switch).

4. U.S. Pat. No. 3,303,476 (channel).

5. U.S. Pat. No. 3,336,582 (CPU channel commands to control unit).

6. US. Pat. No. 3,372,378 (a switching system for a data processing system).

7. U.S. Pat. No. 3,400,371 (a CPU).

8. U.S. Pat. No. 3,550,133 (a channel).

9. U.S. Pat. No. 3,377,619 (polling in a channel including select out).

10. Commonly assigned patent application Cormier et al., Ser. No. 101,079, filed Dec. 22, 1970, entitled Command Retry Control by Peripheral Devices, now U.S. Pat. No. 3,688,274.

BACKGROUND OF THE INVENTION The present invention relates to data processing systems having peripheral device subsystems and particularly to concurrent diagnostics as between a data processing system and the peripheral subsystem, for con currently diagnosing the present operational capability of the peripheral subsystem.

Because of equipment complexities and high performance operating capabilities, data processing systems, and particularly peripheral device subsystems, are periodically analyzed for proper operational status and capabilities. Also, when an error is introduced into the data processing system, apparently by a peripheral device subsystem, certain diagnostic procedures should be invoked for diagnosing the cause of the error so that corrective maintenance can be expedited. In most prior systems, diagnostics relating to a peripheral device subsystem, such as a printer system, magnetic tape subsystem, disk system, drum system, communication system, and the like, either require dedication of a central processing unit (CPU) for diagnosing the present operational capabilities of the peripheral device subsystem (control mode) or that the peripheral device subsystem be completely disconnected from the data processing system and be operated in a diagnostic mode by maintenance personnel (off-line mode). The above procedures, while effective to perform the diagnostics and the maintenance, are quite expensive because: (1) the cost per hour of a data processing system is extremely high; therefore, to assign the entire data processing system for maintaining one peripheral device subsystem is a very expensive procedure. (2) Disconnecting a peripheral device subsystem from a data processing system in many instances may require the data processing system to be stopped while the peripheral device sub system is disconnected. This means additional start-ups and, again, a waste of data processing system total time which becomes expensive. Further, no portion of the peripheral device subsystem is then available for any usage by the data processing system. Maintenance personnel must slowly diagnose the operational status of the peripheral device subsystem without the assistance of automated analysis generally available through a CPU. While some automatic test equipment may be employed, the analysis performable by a CPU usually is much greater than that which can be performed by test equipment. Again, once the subsystem has been diagnosed, it must be reconnected to the data processing system. (3) While disconnecting a peripheral device subsystem from a data processing system may be effective to diagnose operational status of the peripheral device subsystem, some errors can occur in the interface portion. Such disconnection may or may not detect such error-causing conditions. Accordingly, it is highly desirable that concurrent diagnostics be performed on a peripheral device subsystem by a data processing sys tem.

As used in this application, the term concurrent mode" indicates that the data processing system has other tasks or jobs in the system that are active and share system facilities with the diagnostic programs and procedures. This does not necessarily indicate that a given CPU will operate simultaneously on a data processing job or task and a diagnostic job or task. Such jobs or tasks may be interleaved within the CPU with the peripheral device subsystem diagnostics being performed simultaneously with data processing systems or other operations being performed by other subsystems or CPUs.

Quiescent mode means that all operations with respect to a peripheral device subsystem are complete except those initiated directly or indirectly by an OLT (on-line test) such that the peripheral device subsystem is dedicated to diagnostics initiated by the OLT. The CPU may be still operating in a concurrent mode.

On-Line Test (0LT) A computer program in a CPU designed to initiate diagnostic procedures in a pcripheral device subsystem upon command from an operating system within the CPU. Such OLTs supervise diagnostic procedures.

On-Line Test Executive Program (OLTEP) The interfacing program between the CPU operating system and OLT's. It is a supervisory program effecting proper sequencing of diagnostics effected by OLT's.

Control Mode A peripheral device subsystem is entirely dedicated to diagnostics. The 0LT responds to all communications with the peripheral device subsys' tems and operates to the peripheral device subsystem via OLTEP and can act in the supervisory mode. 0LT restricts its activities to those devices in the peripheral device subsystem assigned to it by and through OLTEP before entry into the control mode. Entry of control mode usually requires a console entry and an 0LT request. Exit from either the quiescent or control mode is by initiation from a request via the console into OL- TEP.

Accordingly, for concurrent diagnostic purposes, computer programs have been established including an on-line test executive program (OLTEP) for initiating and supervising concurrent diagnostic procedures. Some of the test requirements to date have required the device being diagnosed to be off-line for effecting a full test of the operating capabilities. Partial tests have been operated on a concurrent mode for a limited number of device operating characteristics. Limited testing on a concurrent basis does not provide sufficient meaningful diagnostic information for minimizing down time of a data processing system. Accordingly, it is very desirable and important that concurrent diagnostic capabilities be enhanced.

SUMMARY OF THE INVENTION It is an object of this invention to provide enhanced concurrent diagnostic procedures for interface checking, status reporting, enable/disable, tag signals, and the like.

A peripheral device subsystem utilizing the teachings of the present invention includes means for performing signal processing or data processing operations in connection with a data processing system. Additionally, means are provided for generating operating condition indications responsive to channel commands to esablish conditions within the subsystem representative of operating conditions not permissible during normal signal processing operations. The above usually follows a SET DIAGNOSE channel command which initiates a diagnostic mode within the peripheral subsystem. Preferably. chaining to an OLT operated CPU is required. During such diagnostic mode, a series of channel commands are issued by the CPU to the peripheral device subsystem forcing stacking status, forcing a falsely indicated control unit busy (CUB) or device busy (DVE BSY). and initiating enable/disable operations and checking response of the peripheral subsystem to nonstackable status as well as to device and I/O controller stackable status. Dedication of the interface between a data processing system and a peripheral device subsystem is performed on a concurrent basis for diagnosing responses and actuations of the peripheral device subsystem with respect to such interface.

The foregoing and other objects, features, and advantages olthe invention will be apparent from the follow ing more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

THE DRAWINGS FIG. 1 is a simplified flowchart showing a sequence of concurrent testing usable in connection with the present invention.

FIG. 2 is a simplified operating system diagram illustrating the broad aspects of the present invention.

FIG. 3 is a simplified block diagram of a system incorporating the teachings of the present invention.

FIG. 4 is a simplified logic block diagram of an I/O controller usable with the FIG. 3 illustrated system.

FIG. 5 is a simplified logic block diagram of a micro processing unit (MPU) usable with the I/O controller illustrated in FIG. 4.

FIG. 6 is a simplified block diagram of microprograms resident in the FIG. 5 illustrated microprocessor used to operate the FIG. 3 illustrated peripheral device subsystem.

GLOSSARY OF ABBREVIATIONS AND ACRONYMS Address Address In (a tag signal supplied by an I/O controller indicating address signals appear on CBI) ADDR ADDRI ADDRO Address Out (a tag signal ALU BKWD ELK INT BLK UC BOC BOR BOT CBI CBO CCW CHNI, ('MI) CMDO CPU

CTI

CTO

CU CUB DE DE? DEPRIME DIAG DIAGNOSE FWD GENRST IBG IC IDLEPEND MPU MPUX MPUY MTU

NOP

OLT

OLTEP indicating address signals are being sent in bus out lines) Arithmetic-Logic Unit Backward Block Interrupt (IIO controller flag blocking SUPPRII Block Unit Check tI/O controller flag blocking UC status after a burst operation) Branch on Condition Beginning of Record (remains active during entirety of record readback signal envelope) Beginning of Tape Channel Bus In tlines for carrying data signals from l/O controller to CPU via INTFX) Channel Bus Out (lines for carrying data signals from a channel to an IIO controller) (hannel ('ontrol Word Channel (ommand (a net of control signals) Command Out (a tag signal telling an l/O controller to change operation in accordance with predetermined criteria) Central Processing Unit Channel Tag In (a set of lines for tag signals supplied from an [/0 controller to a data channel concerning the interpretation of other signals supplied over CBII Channel Tag Out (a set of lines for tag signals supplied from a data channel to an I/O controller interpreting other signals supplied over CBO) Control Unit; an l/O Controller Control Unit Busy la tag signal) Device End (a tag signal from an l/O device indicating end of an operation) Device End Prime [see below) Device End Prime (a flag signal in a memory unit indicating a data channel has previously requested access to an [/0 device. Upon receipt ot'a device end (DE), iiignalii are supplied to the channel to provide accent to the IIO device) Diagnostic A command ordering an I/O controller to enter a diagnostic mode of operation.

Forward General Reset lnterblock Gap Instruction Counter A wait routine for the channel microprogram unit used to wait for further instructions from a data channel A microprogram used to scan for DEPRIMES Information Handling System Interface Circuits Input/Output or Input/Output Device l/O System (a CPU program operating under OS and added to control l/O operations) Instruction Register Local Store Register Multiple Interface Switch Microprogrammable Unit Microprogrammable Unit No. X

(used in connection with a data channel) Microprogrammable Unit No. Y

(used in connection with an IIO device) Magnetic Tape Unit No Operation (do-nothing command) On-Line Test (a CPU program for exercising and testing a peripheral device connected to the CPU] On-Line Test Executive Program (a controlling program for OLT's) OP Operation OPIN Operation In (a tag signal] OS Operating System (a CPU control program) RES Reserved ROS Read Only Store RST Reset 5 RTN Return SDI Subsystem Device Interface (a multiplexing switch selectively connecting several CU's to a plurality of I/O devices) SELO Select Out (a tag signal from channel to CU attempting a [0 selection [connection)) SELRST Selective Reset SFBKWD Space File Backward SFFWD Space File Forward SIO Start 1/0 (a command initiating an M0 OP) SPACE OP An MTU Space Operation [moves or spaces tape] STAT Status STATIN Status In ta tag signal indicating CBI has a status byte) STIN Status In (see STATIN) STS Status SUPPRI Suppressihle Request In ta tag signall SUPPRO Suppress Out [a tag signal) SVCI Service In [a tag signal) SVCCI Service Out (a tag signal) TACH Tachometer TAPE OP Tape Operation TCB Task Control Buffer TIO Test I/O TM Tape Mark TU Tape Unit, also MTU TUADDR Tape Unit Address Register TUBI Tape Unit Bus ln TUBO Tape Unit Bus Out TUTAG Tape Unit Tag Register XA Exchange Register XA XB Exchange Register XB YA Exchange Register YA YB Exchange Register YB GENERAL PROCEDURE Referring now to FIG. 1, the general procedure followed by a data processing system and a peripheral device subsystem for effecting concurrent diagnostics using the present invention is explained. First, a CPU at 100 supplies a SET DIAGNOSE channel command to the peripheral device subsystem for initiating diagnostic mode in the connected subsystem. it then forces the subsystem to be chained to the DIAGNOSE command such that no other data processing system can interrupt the diagnostic procedures and thereby introduce errors inadvertently into the interrupting data processing system. The SET DIAGNOSE command is initiated by an 0LT via OLTEP to a channel processor. The subsystem is responsive to the command and its CCW to establish a diagnostic mode in accordance with the CCW as has been well known. Upon completion of step I00, the peripheral device subsystem is ready to perform concurrent diagnostics.

CPU then sends diagnostic commands to the periph- 5 era] subsystem at 101. This includes forced indications in the I/O controller with regard to I/O devices, the control unit (CU), and to an M18 (multiple interface switch). Other indications, as well, may be forced for indicating operating status for diagnostic purposes, as will become apparent. At the end of step 101, the peripheral device subsystem has been set for diagnosing responsiveness to selected input/output commands and operational status with respect to certain selected channel commands.

The CPU then supplies one or more chained I/O commands at 102. At 103, after the connected peripheral device subsystem has responded to the 1/0 commands supplied at 102, the CPU checks the forced indications and command responses for diagnostic purposes. In accordance with the 0LT, steps I02 and 103 may be repeated. Alternatively, step 101 may be reinitiated for performing a second concurrent diagnostic procedure. Chaining may be maintained as steps 10!, I02, and 103 and repeated for different operating diagnostics. It may be desirable for fully utilizing the concurrency of the diagnostic procedures to break the chaining at 104 for permitting interleaved data process ing operations. That is, the concurrent diagnostics may be performed in connection with one or two peripheral devices. The other devices are available for data processing operations, and it may be desirable to inter leave the diagnostics with the data processing operations at the subsystem level in order to reduce diagnostic cost to the data processing system. Accordingly, when the chain is broken at 104, other programs within the operating system or other data processing systems connected to the peripheral device subsystem can initiate data processing operations. After the chain is bro ken at 104, step may be repeated for a subsequent diagnostic, with the steps 100, 10], 102, and 103 also repeated. Finally, after the concurrent diagnostics, as requested by an initial program load (IPL) operating through OLTEP, the status is logged in CPU at 105 and probably printed out for use by maintenance personnel assigned to the data processing subsystem. The programming exits at 106 completing the diagnostic task.

SYSTEM ORGANIZATION Referring to FIG. 2, the environment in which the present invention may be practiced is shown in simplified form. CPU 110 has an operating system such as 05/360 or 08/370 at 111. OS is an executive which calls in object programs 112 for performing data pro cessing operations, as is well known. The input/output program module "3 (I08) program connects a channel processor 114 to OS 1H for effecting input/output operations. Channel processor 114, in turn, communicates with one or more peripheral subsystems 115 which performs the actual l/O operations. The peripheral subsystem additionally, through MIS, is connectable to another CPU 116 which is organized in the same manner as CPU 110. Additionally, CPU 110 has a set of diagnostic programs 117 which includes OLTEP and a set of OLTs. The OLTs may be resident on a disk subsystem (not shown) and callable into magnetic core memory of CPU 110 upon initiation by an IPL. Once an OLT is resident in CPU "0, it calls in operation of peripheral subsystem 115 through the programmed and hardware chains just described. The OLT controls CPU 110 just long enough to initiate operations of peripheral subsystem 115 during a diagnostic mode. During such diagnostic mode, channel processor 114 may be dedicated to the diagnostic procedure. Additionally, CPU I10 may have a plurality of such channel processors. In the alternative, channel processor 114 may service several I/O subsystems with each subsystem being, in turn, dedicated to an 110 function such as concurrent diagnostic or a data processing operation. Each channel processor 114, of course, services several peripheral subsystems, only one of which is shown in FIG. 2.

PERIPHERAL SUBSYSTEM HARDWARE CONFIGURATION Referring now to FIG. 3, the interface circuits be tween CPUs 110 and 116 and the peripheral device subsystem, including I/O controller 11, are shown in simplified logic form. Portions of the interfacing circuits pertinent to the practice of the invention are brought out in some detail, while the other interfacing circuits not pertinent to the practice of the present in vention, but necessary for effecting interfacing, are shown as a single block in each section. The circuitry represented by logic blocks 150 and 151, respectively. in interface A and B circuits 152 and 153, has been used before in a similar two-channel connection between I/O controller 11 and a pair ofchannels I14 and 118. Interface circuits A and B are connected to controller circuits 154 (FIGS. 4 and 5) via MIS (multiple interface switch) 155. MIS 155 selectively connects circuits 154 to CPU via interface A circuits 152 and channel (A) 114, or to CPU 116 via interface B circuits I53 and channel (B) 118. Additionally, a neutral position is employed. Channels A and B are connected to other peripheral systems in accordance with known data processing techniques.

l/O controller 11 is connected to a plurality of I/O devices via a set of cables 12 through a subsystem device interface (SDI) 157. SD1157 may be constructed in accordance with the teachings of the patent to E. W. Devore, US. Pat. No. 3,372,378. In accordance with that patent, additional controllers 158 and 159 are selectively connectable to the plurality of I/O devices through SDI 157. In turn, CU's 158 and 159 may have separate MISs for connecting to a plurality of CPUs 160.

In accordance with known data processing techniques, any of the CPUs 110,116, or 160 can connect to any of the I/O devices via SDI 157. In practicing the present invention in the illustrated environment, concurrent diagnostics on any of the I/O devices and CUs 11, 158, and 159 may be initiated and supervised by any of the connected CPUs. That is, two of the CPUs 160 may perform diagnostics on CU 158 on a concurrent basis with other tests in the respective CPUs. Additionally, because of SDI 157, such CPUs can perform concurrent diagnostics with respect to any of the H0 devices connected to SDI 157. In a similar manner, CPUs 110 and 116 can, on a concurrent basis, perform diagnostics on I/O controller 11 and any of the I/O devices. The same is applicable to CU 159 and the other CPUs 160.

Before proceeding to the description of the portion of the logic pertaining to practicing the invention in the illustrated environment, the operation of M18 155 as presently employed in several data processing systems is briefly described. The function of M13 155 is that of a multiple-pole, triple-throw switch 165. Effectively, all of the buses and cables interconnecting channels 114 and 118 with U0 controller 111 are switched by 165 through electronic means of known design. In a first position at A, switch 165 interconnects channel 114 to I/O controller circuits 154. At position C (the neutral position), circuits 154 are disconnected from channels 114 and 118. At position B, channel 118 is connected to circuits I54. Switch 165 is actuated by request from channels 114 and 118 as initiated by CPUs 110 and 116. Since CPUs 110 and 116 operate asynchronously,

two requests can he received by MIS at the same time. MIS has priority circuit 166 for assigning priority to one of the two requests. The requests are manifested in the illustration by a select out (SELO) tag signal supplied by channels 114 and 118, respectively, over cables 168 and 169. SELO is supplied from those cables to priority circuit 166 via lines 171 and 172. Additionally, SELO is also supplied to logic circuits 150 and 151 as will become more apparent. Priority circuit 166 responds to SELO on lines 171 and 172 to selectively set selector latch 173 and reset neutral indicating latch 174. For example, if latch 174 is in the active condition, switch is to terminal C. Upon receiving SELO, priority circuit 166 resets latch 174 to the inactive condition and simultaneously sets latch 173 either to A or B for selectively moving switch 165 to the A or B terminals thereby connecting one of the two interfaces to circuits 154. In the illustrated system, interface A has priority; hence, iftwo SELOs are received simultaneously, priority circuit 166 sets latch 173 to condi tion A. As a result of this selection, an initial selection sequence for channel 114 is performed by circuits 154. A control unit busy (CUB) signal is supplied to channel 118 indicating the subsystem is not available. Upon completion of an I/O operation, circuits 154 through microprogram means supply a control signal over cable 176 and thence line 177 setting latch 174 to N, thereby moving switch 165 to terminal C. The condition of latch 173 then is ignored until another SELO is received by priority circuit 166. Under chained opera' tions, circuits 154 are inhibited from setting latch 174 to the active condition, hence, maintaining the operational state of latch 173 in accordance with its setting by circuits 166.

Once M18 165 has been actuated to terminal A or B, SELO is supplied through switch 165 to cable 179, hence, over line 180 to microprocessor circuits within circuits 154 as later described for trapping same to an initial selecting sequence. SELO also travels to interface A and B circuits 152 and 153, logic 150 and 151.

Circuits 154, which include a microprocessor, in response to SELO trap on line 180 supply an address in (ADDRI) initiating signal over cable 176 to either interface circuits 152 or 153 in accordance with switch 165 setting. The respective logic circuits 150 and 151 generate the ADDRI signal for supplying it to the respective channels. Simultaneously, the CUB latches 182 and 183 in the other interface circuits are set to the active condition. These latches supply an activating signal to the encoding circuits 184 and 185 which supply CUB to the respective channels. Encoders 184 and 185 are actuated by a later-described status in (STATIN) signal generated by activity in circuits 154. STATIN indicates that the set of signals on channel bus in (CBI), later described, indicates the status of the response of the I/O subsystem to a request by the activating channel. In this regard, both interface circuits 152 and 153 include STATIN generators 188 and 189 which generate code permutations for CBI, respectively, for chan nels A and B in response to instructions received from circuits 154. STATIN is simultaneously supplied with the code permutations for indicating status of the subsystem.

STATIN generators 188 and 189 generate the STA- TIN signal through OR circuits 190 and 191. In usual data processing operations, logic circuits 150 and 151 respectively generate the STATIN signals. In certain situations, AND circuits 192 and 193 generate a STA- TIN signal. Switched SELO on line 180 is one input to both AND circuits. This indicates that the STATIN tag is generated in response to the SELO after M18 155 has assigned priorities and effected operations of switch 165', i.e., STATIN is not generated until circuits 154 can be connected to the selecting channels. The other inputs to AND circuits 192 and 193 are respectively supplied by OR circuits 194 and 195.

One input signal to both OR circuits 194 and 195 is supplied over lines 197 and 198 entitled "ARM CUB. ARM CUB enables a CUB response to a channel to which the subsystem is chained. Under normal operations, CUB can never be issued to a channel to which the subsystem is chained. This is a technique in concurrent diagnostics enabling a CPU, through its channel, to verify operation of the CUB circuits in the subsystem.

STATIN is also activated whenever circuits 154, either upon their own initiation or upon receipt of a channel command (including a CCW), perform a general or selective reset. During such a reset operation, an activating signal supplied respectively over lines 200 or 201 to supply STATIN to the initiating channel such that the status, as a result of the reset, can be supplied over CBI for analysis by the respective CPUs. Additionally, STATIN is generated in response to an SELO for presenting initial status over CBI as detected by AND circuits 202 and 203, respectively, for the two interfaces. These AND circuits are responsive to AB latch 173 being in the appropriate signal state, latch 174 indicating a not neutral connection of switch 165, and a STATIN generating signal received from circuits 154.

HO CONTROLLER 11 AND ITS RELATIONSHIP TO THE SYSTEM l/O controller 11 operates with the channel described in the Moyer et al., US. Pat. No. 3,303,476. FIGS. 1 and 3 of that patent describe all tag signals used herein except SUPPRESSIBLE REQUEST IN which is defined with respect to MPUX (channel MPU) microprograms. It also assumes that the interface between the controller and the I/O devices follows a similar busout, but-in, tag-line arrangement. In addition to the functions described in the Moyer et al. patent supra, a tachometer input line is provided to I/O controller 11, as later described.

The term CPU" is hereafter used to include the channel portions of data processors. 110 controller 11 provides control for exchanging informationbearing signals between CPUs and I/O devices, such as magnetic tape units (MTUs) via cable 12 (FIG. 4).

I/O controller 11 has three main sections. MPUX is a microprogrammable unit (MPU) providing synchronization and control functions between the 110 controller11 and channels 114 and 118. MPUY performs sim ilar functions with I/O devices via SDI 157. In a magnetic tape subsystem, MPUY provides motion control and other operational related functions uniquely associated with the device. The third section is data flow circuits 13, which actually process the information-bearing signals. Data flow circuits 13 may consist of entirely a hardware set of sequences and circuits for performing information-bearing signal exchange operations. In an I/O controller associated with a magnetic tape recording system, such data flow circuits include writing circuits for both PE and NRZI, readback circuits for both encoding schemes, deskewing operations, certain diagnostic functions, and logging operations associated with operating a magnetic tape subsystern.

Since MPUX and MPUY are independently operable, each having its own programs of microinstructions, program synchronization and coordination are provided. To this end, MPUX has exchange registers 14 while MPUY has exchange registers 15. The signals from the MPUs temporarily stored in these registers are supplied directly to data flow circuits l3 for effecting and supervising data flow and signal processing operations. Additionally, such signals are simultaneously provided to the other MPU. That is, register 15 supplies MPUY output signals to MPUX and register 14 supplies the MPUX output signals to MPUY. The respective MPUs under microprogram control selectively receive such signals for program coordination.

The channels exchange control signals with MPUX over CTO (channel tag out), CTI (channel tag in), CBO (channel bus out), and CBI, plus trap control line 17. When the trap line is actuated, MPUX aborts all present operations and branches to a fixed address for analyzing signals on CBO. These signals force MPUX to perform channel commands or selected functions. In a similar manner, MPUX has trap control line 18 extending to MPUY. MPUY responds to an actuating signal on line 18 from MPUX in the same manner that MPUX responds to a trap signal on line 17. MPUY, in addition to exchanging control signals with I/O devices, also has trap line 21 for controlling an I/O device in a similar manner. All information'bearing signals are processed through data flow circuits 13 via full-duplex cables 23 and 24.

Data flow circuits [3 have CBI lines 30 and CBO lines 31. Each set of lines has a capability of transferring one byte of data plus parity. Similarly, tape unit bus in (TUBI) lines 32 transfer signals to data flow circuits 13 and MPUY to the I/O devices via SD] 157. Tape unit bus out (TUBO) lines 33 carry informationbearing signals for recording in MTUs plus commands from MPUY and MTU addresses from MPUX. Status signals are supplied both to MPUX and MPUY over status cables 34 and 35. Velocity or tachometer signals supplied by the selected and actuated MTU are received over line 36 by MPUX, MPUY, and data flow circuits 13.

MPUX has output bus 40 (also termed 8 bus) supplying signals to its exchange registers 14. These include branch control register 41, register XA, and register XB. Output bus 40 is also connected to the channel exchanging registers 42. These registers are CTI and CBI. CBI is channel bus in, while CTI is channel tag in. CTl transfers the tag signals from I/O controller 11 to CPU as described in the Moyer et al. patent and other control signals for interfacing operations.

Additionally, CBO gate 43 receives bytes of data for data flow circuits 13 and for MPUX. Gates XA and X8 similarly gate exchange signals from the MPUY exchange registers 15. Gate XA receives the control signals from register YA while gate XB receives exchange signals from register YB. CBI register is shared by MPUX and data flow circuits 13. The CBI lines are multiplexed in accordance with the Moyer et al. patent.

CTI supplies tags indicating what the bus in signals mean.

Signals in TUBO register output lines 33 are interpreted by the MTU's in accordance with the signals in TUTAG (tape unit tag) register.

External signals are supplied to MPUX and MPUY via external registers 50 and 51, respectively. Such external signals may be from another I/O controller, from a maintenance panel, communication network, and the like. Also, hardware detected errors are lodged in register 52 for sampling by MPUX.

I/O controller 11 has an efficient initial selection process. MPUX responds to a channel SELO request for service of an MTU to provide the MTU address over output line 40 into TU address register 60; from there, the address is sent to all MTU's. The appropriately addressed MTU responds to MPUY that the selection is permissible or not permissible. If permissible, a connec tion is made; MPUY notifies MPUX via register YA. MPUX then completes the initial selection by responding to the requesting channel via CTI and M 155. Data processing operations then ensue.

MICROPROGRAMMABLE UNITS (MPU'S) The MPUs contain microprograms which determine the logic of operation of HO controller 11. MPUX contains a set of microprograms in its control memory designed to provide a responsiveness and data transfers with the channels. In a similar manner, MPUY contains a set of microprograms for operation with the various MTUs. Registers l4 and 15 contain signals from the respective microprograms which serve as inputs to the respective programs for coordinating and synchronizing execution of various functions being performed. A better understanding of how the microprograms operate the hardware is attained by first understanding the logic construction of the MPUs which are constructed in an identical manner.

Referring more particularly to FIG. 5, an MPU usable in l/O controller 11 is described in a simplified block diagram form. Data transfers are serially in bytes ofeight bits each. The microprograms are contained in read only store (ROS) control memory 65. While a writable store could be used, for cost-reduction purposes, it is desired to use a ROS type of memory. The construction and accessing of such memories are well known. The ROS output signal word, which is the instruction word, is located by the contents of instruction counter (IC) 66. IC 66 may be incremented or decremerited for each cycle of operation of MPU. By inserting a new set of numbers in IC 66, an instruction branch operation is effected. The instruction word from ROS 65 is supplied to instruction register (IR) 67 which staticizes the signals for about one cycle of operation. The staticized signals are supplied over cables 68 and 69 to various units in MPU. Cable 68 carries signals representative of control portions of the instruction word, such as the operation code and the like. Signals in cable 68 are supplied to IC 66 for effecting branching and instruction address modifications. Cable 69, on the other hand, carries signals representative of data addresses. These are supplied to transfer decode circuits 70 which respond to the signals for controlling various transfer gates within MPU. The other portions of the signals are supplied through OR circuits 71 to arithmetic logic unit (ALU) 72. In ALU 72, such signals may be merged or arithmetically combined with signals received over B bus 73 for indexing or other data processing operations. MPU has local store register memory (LSR) 75 accessible in accordance with the address signals carried over cable 68. Address check circuit 76 verifies parity in the address. The address signals may also be used in branch operations. AND circuits 77 are responsive to transfer decode signals supplied from circuits through AND circuits 78 to transfer the address signals in an instruction word to IC 66. Such transfer may be under direct control of the operation portion of the instruction word as determined by transfer decode circuits 70 or may be a branch on condition (BOC) as determined by branch control circuits 79 which selectively open AND circuits 77 in accordance with the conditions supplied thereto, as will become apparent.

The data flow and arithmetic processing properties of the MPU center around ALU 72. ALU 72 has two byte inputs, the A bus from OR circuits 71 and B bus 73. ALU 72 supplies output signals over cable 80 to D register 81. D register 81 supplies staticized signals over D bus 82 to LSR 75. Instruction decode circuits 83 receive operation codes from IR 67 and supply decoded control signals over cable 84 to ALU 72 and to AND circuits 78 for selectively transferring signals within MPU.

ALU 72 has a limited repertoire of operations. Instruction decode 83 decodes four bits from the instruction word to provide 16 possible operations. These operations are set forth in the Instruction Word List below:

TABLE I Instruction Word List Op Code Mnemonic Function 0 STO Store constant in LSR A set to 0 I STOH Store constant in LSR, indexed addressing 2 BCL Match with Field 1, branch to Addr in Field 2 3 BCH Match with Field I, branch to Addr in Field 2 4 XFR Contents of one selected LSR location is transferred to selected register or selected input is gated to one selected LSR location 5 XFRH See XFR above plus indexed addressing 6 BU Branch to 12-bit ROS address in instruction word 7 00 Notused illegal code 3 A OR'd with B, result stored in LSR 7S 9 ORM A ORd with 8, result not stored A ADD A plus B, sum stored in LSR B ADDM A plus 8, sum not stored C AND A ANDed with 8, result to LSR D ANDM A ANDed with B, result not stored E X0 A EXCLUSIVE OR B, result to LSR 75 F XOM A EXCLUSIVE OR B, result not stored In the above list, the letter A means A register 85, B is the B bus, and the mnemonics are for programming purposes. The term "selected input" indicates one of the hardware input gates (92, 94, 96, 98) to the ALU output bus 80. The term selected register" indicates one of the "hardware registers in MPU. These include the interconnect registers 14 and 15 (FIG. 4), tag register 74, bus register 99, address register 60, and

IC 66. Note that the transfers from LSR 75 to these selected registers are via B bus 73. In FIG. 4, the B bus for MPUX corresponds to cable 40, while the MPUY B bus is cable 40A. Registers 14 receive signals via AND circuits 86 and 87. In MPUY, AND circuits 86 and 87 supply signals to exchange registers 15. Branch control 79 in FIG. is the internal branch control. Branch controls 41 and 41A of FIG. 2 supply their sig nals respectively over cables 88 and 87A to the respective MTUs. These branch controls are separate circuits. Tag register 74 in FIG. 3 for MPUX corresponds to CTI register in the channel exchange registers 42. For MPUY, it corresponds to TUTAG register connected to SDI 157. In a similar manner, bus register 99 for MPUX is register CB1 in channel exchanging registers 42, while in MPUY it is register TUBO. Address register 60 of FIG. 5 corresponds to TU address register 60 of FIG. 4. MPUY address register 60 is not used.

Status register 89 has several output connections from the respective MPUs. It is divided into a highand low order portion. The highorder portion has STAT (status) bits 0-3, while the low-order portion has STAT bit 0 plus STAT bits 4-7 (referred to as STAT A through STAT D, respectively). The low-order por tion is supplied to the branch control 79 of the other MPUs. The bits 0 and 4-7 are supplied to the data flow. Bit 7 additionally is supplied directly to the ALU 72 of MPUY as indicated by lines 90 in FIG. 4. This corresponds to a self-trapping operation which will be later described. Interpretation of the STAT bits is microprogram determined.

The signal-receiving portions of each MPU are in four categories. First, bus register 91 is designed to receive tags and data bytes for MPUY; this corresponds to CEO register 43 of FIG. 4. An MPUY bus register 91 is TUBI register. AND circuit 92 is responsive to the transfer decode signals from circuits 70 to selectively gate bus register 91. From thence, the data bytes are supplied to LSR 75. Secondly, D register 81 also receives inputs from hardware error register 93 via AND circuits 94. Hardware error signals (parity errors. etc.) are generated in circuit 95 in accordance with known techniques. Thirdly, AND circuits 96 receive external data signals over cable 97A for supplying same to D register 81 under microprogram control. Fourthly, interchange registers 14 and 15 respectively supply signals to pairs of AND circuits 98 which selectively gate the interchange signals to D register 81 under microprogram control. The receiving microprogram controls the reception of interchange signals from the other MPU.

Generally, the outgoing signals from each MPU are supplied via B bus 73, also a main input bus to ALU 72. The signal-receiving bus is the D bus, which is the input bus for LSR 75 and the output bus for ALU 72.

Since ALU 72 has a limited repertoire of operations, many of the operations performed are simple transfer operations without arithmetic functions being performed. For example, for OP code 4, which is a transfer instruction, the contents of the addressed LSR are transferred to a selected register. This selected register may be A register 85 in addition to the output registers. To add two numbers together in ALU 72, a transfer is first made to A register 85. The next addressed LSR is supplied to the B bus and added to the A register contents with the result being stored in D register 81. At

the completion ofthe ADD cycle, the contents or result of D register 81 are stored in LSR 75. Ifit is desired to output the results of the arithmetic operation, then another cycle is used to transfer the results from LSR over B bus 73 to a selected output register such as one of the interchange registers or bus register 99.

In FIG. 5, the input to D register 81 is either cable 44 or 44A of FIG. 4. Hardware error circuits 9S and error register 93 of FIG. 5 correspond both to the hardware error circuits 52 and 52A of FIG. 4. External cables 97A receive signals from the external registers 50 and 51 respectively for the two MPUs.

AND circuits 98 of FIG. 5 correspond to the gates XA, XB, YA, and YB of FIG. 4.

Each MPU is trapped to a predetermined routine by a signal on trap line 17 or 18, respectively; the trap signal forces IC 66 to all zeroes. At ROS address 000, the instruction word initiates X-trap routine or Y-trap routine (FIG. 6). For reliability purposes, it is desirable to force MPUY to inactivity. This means that clock or oscillator 48 is gated to an inactive state. During normal operations, clock 48 supplies timing pulses to advance IC 66 and coordinate operations of the various MPUs as is well known. Whenever MPUY has finished its operations, it sets STAT D in register 89. STAT D indicated MPUY has finished its operations as requested by MPUX. The STAT D signal sets hold latch 99A indicating that MPUY is inactive. Hold latch 99A gates clock 48 to the inactive condition. When MPUX traps MPUY, not only is 1G 66 preset to all zeroes, but hold latch 99A is reset. Clock 48 is then enabled for operating MPUY.

MICROPROGRAMMING GENERALLY FIG. 6 shows general relationships between the micro-routines of MPUX and MPUY. This showing is greatly simplified to give a general impression of how the micro-routines cooperate to perform I/O controller functions. Many of the functions performed by these micro-routines have been performed before in other I/O controllers, usually by hardware sequences. Some micro-routines of lesser importance to the present invention have been omitted for clarity. The described routines were selected to illustrate the operating relationships of MPUX, MPUY, data flow circuits l3, MTU's, and CPU in evaluating subsystem performance by concurrent diagnostics as more clearly brought out later.

X-idlescan and Y-idlescan 121 monitor pending status, interrupt status, and provide intercommunication between the two MPUs for ascertaining availability of the I/O devices. X-idlescan 120 includes trapping MPUY via Y-idlescan 121 for polling [/0 devices via SDI 157 to determine availability of an addressed MTU. Included in X-idlescan is a wait routine which idles MPUX until trapped by a channel. The channel traps MPUX to ROS 65 address 000. At MPUX ROS address 000, X-trap 122 begins. During the execution of X-trap routine 122, MPUY is trapped to ROS address 000 to later execute Y-trap routine 123. In X-trap 122, CTO is sensed for initial selection. If the initial selection tag is active, X-trap routine branches the microprogram to X-initial selection 125. If there is no initial selection, then either X-RESET 126 or an ALU diagnostic within diagnostic routine 127 is performed. Diagnostic routine is shown in part in flowchart form in FIG. 7. Upon completion of these functions, X-idlescan 120 may be re-entered to complete MTU scanning operations. Initial selection 125 is responsive to certain hardware errors received at 128 (sensed as described with respect to FIG. 3) to stop I/O controller 11 for indicating detected hardware errors.

During an initial selection, X-polled 129 is entered to further identify the channel request. Also, certain branch conditions are set up in LSR for use later by X- termination 130. MTU address verification may be performed. Upon completion of the branch setups, the X- polled 129 initiates X-status 132. X-status 132 activates CTI to send tag signals to the channel interface indicating controller status in response to the previously received requests. Based upon the branching set up in X-polled 129, the microprogram execution may follow several routes. These primarily end up in X- termination 130 which terminates the MPUX operation. MPUX then scans for further interrupts. With all scanning completed, MPUX waits for further instructions from either channel 114 or I18.

Another routine is service return (SERVRTN) I35 used in conjunction with the channel interface circuits I52 and 153 for timing and control purposes during data transfers. The operation of the above-referred-to data channel in Moyer et al. is implemented by SERVRTN I35. Another possible routine entered from initial selection 125 is X-mode 136, which determines the mode of operation in the controller in response to channel CMDO (command out) signals. X-read type and test 137 is entered in the event the initial selection results in a read operation. X-read type and test 137 traps MPUY to predetermined ROS control memory addresses for initializing a read operation, within MPUY. In a similar manner, X-write 138 is entered and also traps MPUY to another subroutine for initializing a write operation. Error status 139 transfers error information to CPU. This routine is closely associated with initializing l/O controller ll for read and write. Sense 140 is entered in response to a channel sense command. Sensing transfers sense bytes to CPU for analysis. X-termination I30 also traps MPUY in connection with the selecting activated MTU's and for performing other functions in connection with terminating an operation previously initiated through a channel. MPUY micro-routines respond to MPUX microroutines for controlling various MTU's via SDI 157. These micro-routines also transfer information control signals, I/O devices, and SDI 157 to MPUX for retransmittal to channel and CPU. Upon being trapped by MPUX, Y-trap 123 obtains an MPUY ROS address from XB register and then branches to that address. Such ROS addresses are the first instruction address of several MPUY microprograms. For example, one address initiates diagnostic I42. Diagnostic 142 may initiate one of several microprograms for effecting operations in CU 11 or an MTU for diagnostic purposes. Such program connections are not shown.

On the other hand, Y-trap routine I23 may branch to Y-initial selection 148 to initialize MPUY for activity set forth in additional control signals from MPUX in registers 14. This may include an initiation of status 149, termination 147, or Y-idlescan 12]. The MTU operating routines 143-146 may also be initiated from initial selection 148. In addition to exchanging control signals via registers 14 and 15, status information is freely exchanged between the two MPUs for microprogram coordination.

MICROPROGRAM SEQUENCE FOR MPUX ENABLING CONCURRENT DIAGNOSTICS A simplified flowchart later shows microprogram flow for setting and sensing chained and diagnostic flags effecting concurrent diagnostics. MPUY microprograms are subservient to the described microprogram for effecting certain diagnostic functions not necessarily associated with enabling concurrency and, therefore, are not described. LSR in MPUX retains diagnostic and operating flags upon which the microprograms branch to various sequences for effecting the designated concurrent operations. For ease of reference, a partial LSR map for control flags in MPUX LSR 75 is set forth below:

TABLE II Selected Diagnostic Flags Reglltcr and Hit Hag 4-0 [)IAG MODE 4-! HLK INT 4-2 FORCE DVF. BSY 4-3 ARM CUB 4-4 BLK UC 4-5 4-7 Selected Operation Flags Register and Bit Flag 5-0 CHAIN A 5-! CHAIN B 5-2 REW/DSE 5-3 OP COMPLETE 5-4 UNIT CHECK 5-5 ENABLE 5-6 5-7 6-0 OPIN 6-I STATIN 6-2 CUB-A 6-3 CUB-B 6-4 ADDRI 6-5 SVCI 6-6 CUR 6-7 DF. 7-0 DI'LPRIME 8-0 DIiPRIME In the flowchart below, each major sequence step is listed, followed by the description. Entry to the various sequence steps is from the immediately preceding step unless otherwise indicated after the word Enter." Exit from the sequence step is to the immediately following listed sequence step unless otherwise indicated. The function is described in abbreviated form indicating the function performed during the particular step. That is, each step represents several micro-instructions in MPUX, the exact code listing being one of programming design not necessary to practicing the present invention. Following the flowchart, a brief description ties selected steps of the microprogram flowchart into the functions performed for concurrent diagnostics. Reference to particular steps in this flowchart will be by reference to sequence step number.

SEQUENCE STEP Ml X-IDLESCAN Enter From: M19 when 5E STS M16 when CHAIN (entry from M16 only when not chained).

Function: Scans to find pending status in subsystem such as interrupts, device ends, etc.

Exit To: M2 at end of scan or detection of interrupt, device end, or status to be reported to CPU, raise REQIN upon exit; M3 when trapped by channel or hardware.

SEQUENCE STEP M2 X-IDLEPEND (A PART of X-IDLESCAN 120) Enter From: M1; M20 when SUPPRO (M20 entry only when SUPPRO from channel is inactive which indicates channel has completed its sequence).

Function: Wait for channel SELO.

SEQUENCE STEP M3 X-TRAP 122 Enter From: By trap only.

Function: On trap by channel, logic 150 or 151 set branch conditions in branch control 41. Microprogram scans these branch conditions to enter a microprogram corresponding to a channel command.

SEQUENCE STEP M4 INITIAL SELECTION 12S M4A Function: Perform initializing functions as described in patents showing channel operations. Below are particular functions related to concurrent diagnostics as implemented in 1/0 controller 11.

M48 Function: BOC Not Chained, Go to M4C; BOC

Chained, skip M4C, go to M4D (maintain diagnostic mode). (Never chained on first command of a chained sequence).

M4C Function: Reset all LSR diagnostic flags. This is done on first command of any chained sequence initiated by an $10 (start l/O). See remarks of effect on concurrent diagnostics. Since chaining has been broken, CPU is indicating to H controller that the diagnostic procedures have been completed. Accordingly, all diagnostic flangs including BLT INT are reset for enabling usual data processing operations.

M4D Function: Initial status bytes from LSR 75 are transferred to CBI with STATIN activated on CT] in accordance with patents describing channel operations. The chained condition in 1/0 controller 11 is reset if SUPPRO is inactive and continues set if SUPPRO is active. This enables the CPU to either selectively continue the chain or break it after execution of the command in step M5. CUB is activated in the channel interface not chained.

SEQUENCE STEP MS Function: Detect for a rewind (REW) or data security erase (DSE). Exit: 0 exit to M for executing command. 1 continue on testing chain.

SEQUENCE STEP M6 Function: Test for chained condition in an interface.

Exit: 0 exit to M9. 1 continue testing for forcing unusual conditions on interface.

SEQUENCE STEP M7 Function: Test LSR flag to see if device busy (DVE BSY) is to be sent to CPU. 1 exit to M10 for executing command. 0 perform M8.

SEQUENCE STEP M8 Function: Set LSR hold status. This status indicates a free-standing or time-consuming operation to be performed by an l/O device upon completion of initiation of U0 device function. CU will continue to do other things and will not send ending status to channel for device until a DVE is received.

SEQUENCE STEP M9 Function: Set LSR REW/DSE FLG. This indicates to the microprogram that an REW/DSE is being performed by the addressed MTU. There is one flag for each l/O device or MTU. This flag is used during IDLESCAN 120 for checking whether or not the REW/DSE is still being performed by the addressed MTU.

SEQUENCE STEP M 10 Function: Executes channel command. This may be a read, write, sense, or print in accordance with U0 subsystem functions as related to the CPU.

SEQUENCE STEP M11 Function: Sense for REW/DSE. 0 exit to M13 for as semhling ending stat' (do not have to wait for completion ofl/O device operation). 1 exit to M l2.

SEQUENCE STEP M12 Function: Check for REW/DSE.

Exit: 0 device has completed free-standing operation. Return to l for scanning activity of other devices. I wait loop for completion of 1/0 device operation.

DVE from device doing SEQUENCE STEP M14 Exit: 0 not UC, exit directly to M15. 1 UC condition is sensed without a block interrupt. Exit to M14C for adding UC to ending status.

M14C Function: UC sense bit in LSR status byte is set in preparation for sending UC status to channel in CPU.

SEQUENCE STEP M15 Enter: Steps M14A, B, or C.

Function: Transfer status information to CPU. Status byte from LSR is supplied to CB1 while simultaneously STATIN bit is activated on CTl. If SUP- PRO is received from connected channel, the chaining latch in CU is set for continuing the diag nostic or chaining operation.

SEQUENCE STEP M16 Function: Check for chaining condition.

Exit: 0 return to M1 for IDLESCAN operation, i.e.,

all channel commanded functions have been completed. 1 continue on chained operation.

SEQUENCE sTEP M17 Function: Reset all CTls.

SEQUENCE STEP M18 Function: Check for ARM CUB flag. Exit: to M20. 1 exit to M19.

SEQUENCE sTEP M Function: ARM CUB sets flag in LSR 75 for supply ing a CUB signal in response to the next received channel command (note that chained condition is maintained).

SEQUENCE STEP M20 ccived is the first command in a set of chained commands or the only command. Accordingly, the block interrupt flag (BLK INT FLG), as well as all other diagnostic flags, is reset in step M4C. To maintain the BLK lNT FLG during a chained diagnostic operation for preventing the control unit from interrupting with ending device status, all SlOs must have a SET DIAG- NOSE command with a channel control word (CCW) indication BLK lNT FLG being set. This set of operations interlocks the diagnostics from other data processing operations which are operating concurrently. Data processing operations, whether or not chained, do not use SET DIAGNOSE; and, therefore, the BLK INT FLG will never be set during normal data processing operations. Also, upon dropping a chained condition by not supplying SUPPRO, the block interrupt and other diagnostic flags are reset enabling the CU to return to data processing operations. Accordingly, the BLK INT FLG will only be activated from the SET Dl- AGNOSE following an SlO to the beginning of the next 810.

MPUX (ALU-l) PARTIAL MICROCODE LISTING LOC OEUECT sTHT sOuRCE STATEMENT 9850.0..i0iill'l0'.tfiitttttt'l'filtt'l'l'l'lltfiitttl.Oltl'i'ltili'illli CODE 986+ ALU2 Is ALWAYS sLAvEo TO ALUI ANY OPERATION EXECUTED BY ALuz 987+ MUST ALwAY BE INITIATED sv ALUI vIA A XOUTB. THE XOUTB BY ALUI 900+ 'rRAPs ALU2 TO LOCATION 000. ALU2, BEGINNING EXECUTION AT 000, 909 EETCHHs AN INDEX BYTE FROM ALuI AND MOVES IT TO THE INsTRuCI ION 990+: COUNTER. THE INDEX BYTE WILL POINT TO ONE OE THE BRANCH INsTRuCI- I 99 I n IONs I THE BRANCH TABLE. THE SELECTED BRANCH INsT WILL BE 992+ EXECUTED AND THE DESIRED ROUTINE WILL BE ENTERED. WHEN THE 993+ SELECTED ROUTINE COMPLETEs, mm D HILL EE sET INDICATING TO 99a+- ALuI THAT THE DESIRED FUNCTION HAS BEEN COMPLETED. ALU2 WlLL THEN 995+: BE HELD AT LOCATION 000 UNTIL ACTUATED BY ALUI vIA XOUTE TRAP 996+-U'Otlitt'i'tlii'iO."it.0I'i0lli'ttl'tflt'li'lttQQIOOC'UOIO'OIOtI' 000000 5788 999 BYPASS XER HORI 2,XINE FETCH ALUI INDEX 000001 0800 I002 STO sTATING,zERO CLEAR sTAT lHAGE REG 000002 1800 I005 sToH' STATIMG,O CLEAR sTAT IMAGE REG HIGH 000003 0020 100a XER sTATING,sTAT CLEAR ANY OUTSTANDING sTATs 000000 5722 101 l xER WORJQ, IC MOVE INDEX To INsT CTR 000005 6000 I010 NDXTSTB BU EXECTsT3 GO DO ALU 2 CHECKOUT 000006 6000 I01 7 NDXDES Eu EXECDEs H10 NOT OPRTING-Co DEsELECT Tu 000007 6000 I020 NDXPOLL BU EXECPOLL 00 POLL DEvICE FOR sTATus 000008 6000 I023 NDXORsT BU ExECGRsT 00 DO GENERAL REsET 000009 6000 I026 NDxsRsT BU EXECsRsT G0 00 sELECTIvE RESET 00000A 6000 I029 NDXSDE Eu EI-IECsDE GO sET DEvICE END 000000 6000 I032 NDXAERT R0 EXECABRT STOP THE DEvICE IE GOING 00000- 6000 1035 NDXDMR BU EXECDNR 00, D0 DIAG MEAsERE 000000 6000 103a NDxAXEss BU ACCEss 60 GET READ ACCEss TIME 00000E 1990 I001 NDXELAGs XER l-LAGS,XINA BRING IN ELAG BYTE 00000? DNDXSNfiR E LI 0000M 6000 was SRETURNI BU ZAPIM usE ON sENsE RESET t. sEL RESET RETURN 000010 4090 was NDXELAG2 XER w K5 ,XINA GET TUBO MAsK (SET ELAGs In I 000035 IOEOINIIXEsE E U I. .Is' CU DU FORWARD SPACF. FILE 00003 I05I+NUXER$ E u X' 31 00 DH l-RASF TO END uI- TAPEI EDT I 000037 1052+NDxEsR E 0 X' I'I' 00 DO I ORNARD SPACE RECORD 0003 1053*NDXRDI- E U X 33' G0 00 READ IORwARII 00003C OEIHNDXBSF E U x' 3C 00 IX) EACREPACE EI IE 00003E I055+N0XE5R I U X' 3E G0 00 BACKSPACE RICORD 00003A 1056+NDXRDB E U x 3A GO DO READ EACKHARD 00001 3 IO57+NDXWRI E U x' I 3' 00 DO wRITE OPERATION 000020 1058+NDXWTM EQU x 20' GO DO WRITE TAPE MARK 000022 I059+NDXERG EQU x 22' G0 00 ERAsE RECORD GAE 00002E 1060+NDXRHD EQU x 2? 00 DO REHIND 000029 1061 +NDxRwu E u x 29' GO DO REHIND UNLIOAD 0000ED 1062+NDXST5 EQU x'Eo' G0 00 INITIAL sTATus 0 0 1063*NDXSNS EOU X EI G0 00 sENsE 0? 000000 I065 HEGIN CsECT 1066 ALUI HEGIN 106! POWER ON RESET Is CHECKED FIRST To INSURI'. THAT LsRs HAVE G000 1068 PARITY PRIOR To THE ENsuINr; ALU 0P5. 000000 2P1 1070 CHKRSTS BOC EwRHsT,EXEcRsT BRANCH I l-' POHER ON REsEI 00000 I 3C0u I0 II HOC NGENR,NOREsETs BRANCH IE NOT GENERAI REsET 000002 CIEO 1070 AND (TXMAGE,X' FO' CLEAR CHANNEL TAGs 0150 I079 XER CTIHAGE,CTI sET To HARDNARE 000018 000019 0000111 000018 00001C 000010 0O001E 0200 D8 40 310A 5681 S584 2218 2210 1008 CBCD CAFO M018 2381 B180 3021 501:1 3C15 635B 1000 0821 5006 8000 4006 BBCO 2C1? IIJAO C60? 4321 B600 1660 8103 1150 C1FD 10 48 1 109 12AD 294E ZBAD 6034 D000080'.0.0080000800080000: I U FA L'HECK an;0.000000000000000... EACH TIME ALU1 IS TRAPPED TO LDC 0, THE ALU HARDWARE ERROR. REGS ARE TESTED FOR A FAILURE. THE TWO EXCEPTIONS ARE: 0 1 POWER ON RESET 2. A PRIOR FAILURE THAT HAS NOT BEEN CLEAREI) BY A SENSE OP ONCE A FAILURE HAS BEEN DETECTED, THE ALU ERROR REGS ARE SAVED IN LSRS AND WILL REMAIN UNTIL A SENSE OP IS ISSUED. THE ALUFAIL FLAG PREVENTS OVERLAYING THE LSRS WHEN THEY ARE HOLDING PRIOR ERROR DATA THE FIRST SIO/TIO [OTHER THAN SENSE} SUBSEQUENTLY ISSUED TO THE CONTROLLER AFTER AN ALU FAILURE WILL BE UNI CHECKED. SUCCEEDING SIO/TIO'S WILL RECEIVE AVAILABE STATUS IF THE ONLINE PROGRAM CHOOSES TO IGNORE THE INITIALLY UNIT CHECKED SIO/TIO. 00a:nae.usanuonauounaanaouuucuoutannin.naucouanaao'tauunuauuocnanlauu NORESETS STO XOUTAIM,0 CLEAR DATA FLOW CROSSOVER ANDM FLAGSLALUFAIL MASK FOR PREVIOUS ALU FAILURE HOC DREG1 ,ANYMOR BRANCH IF THERE WAS XFR ALU2ERR,EXT FETCH ALU2 HARDWARE ERRORS XFR ALU1ERR,HDWR FETCH ALU1 HARDWARE ERRORS BOC ALUR,HNDLERR BRANCH IF ANY ALU ERRORS ANYMUR 80C ALUR,CLEARIT BRANCH IF ERROR TO CLEAR SETABRT 5T0 XOUTBIM,NDXA8RT-ALU2BRT SET XOUTB IMAGE FOR USE LATER AND FLAGS2,X'C0' CLEAR FRU REGI EXCEPT FAIL FLAGS I AND REQTAGS,ONES-15 MASK ALL REQUEST DOWN XFR REQTAGS,MIST RESET TO HDWE 80C MIFTR,MIFTR12 BRANCH IF MIS AVAILABLE SETHOLDA ORI CTIMAGE,HOLDA RAISE CHAINING HOLD LINE CHKISEL BOC ISEL, INSELCHK BRANCH IF CHANNEL POLL OR SELECT XFR XOUTBIM,XOUTB TRAP ALU2 TO INITIALIZE BOC NGENR,CKSELRST BRANCH IF NOT GENERAL RESET EXECRST BU GENRESET GO DO GENERAL RESET CKSELRST BOC SELRST,SELRTNO DO SELECTIVE RESET ROUTINE. GODOALU BU ALUCHECK DO ALU CHECKOUT.

SELRTNCI BU SELRESET GO DO SELECTIVE RESET HNDLERR STO FRUREG,0 CLEAR SENS FRU REG XFR FLAGS2,AR MOVE FAIL INDICATOR TO ALU A REG XFRH LSR SET HIGH LSR'S ORI FRUREG, 0 MOVE FAIL IND. INTO SENSE FRU REG XFR LSR SET I1) LSRS CLEARIT ORI FLAGS2,ALUFAIL+FORCEUC OTHERWISE SET FAIL FLAGS BOC SELRST,SELRTNO BRANCH IF SELECTIVE RESET XFR (LEAR CLEAR THE ERROR BU SE'IABR'I RETURN TO MAINLINE WHEN INSELCHK IS REACHED WE HAVE BEEN TRAPPED FOR INITIAL SELECTION OR A POLL. IF ADDRESS OUT IS UP-INITIAL SELECTION IS INDICATED. its.uaunauununttuutunantaaaas:nlnntuinnaaaano:oaaunualantnunuoanllant INSELCHK BOC ADROUT,SIORTN BRANCH IF 510. IF NOT, POLL ACC ANDM FLAGS,STATPNDG+STACK TEST FOR PENDING ORASTACK BOC DBUS,POLLED BRANCH IF NOT PNDG OR STACK. BU INTFCHK GO HANDLE PENDING STATUS ac0000:cuuuunauunncoatanuuuucuuntoatauunnaua:uatasutaclnuuutlonuaoaou POLL ACCEPTED. IF STATUS IS PENDING OR STACKED THE PENDING ADDRESS REG IS USED TO VERIFY THE CORRECT CHANNEL. OTHERWISE THE CONTROL UNIT ADDRESS FOR THE CHANNEL POLLING IS MOVED FROM CHANNEL BUS OUT TO THE PENDING ADDRESS REG. IF STATUS IS DUE TO A SECURITY DEVICE END OR DEVICE END DUE TO A PRIME, ALU2 WILL BE SPINNING WAITING TO CLEAR THE DEV END CONDITION IF CHANNEL ACCEPTES STATUS. it0.00.!litttllittt'tittttti'tIUOUOO'UIOUQIUO'UU'IU00008000000008.

ROLLED XFR CURADDR,CHO GEI CU ADDRESS FROM HARDWARE AND PNDADDR X 0F CLEAR HIGH ORDER XFR CURADDR,AR MOVE CU ADDRESS TO ALU INPUT REG ORI PNDADDR,ZERO MERGE DEV AND CU ADDRESSES INTFCHK XFR PNDADDR,CBI MOVE ASSEMBLED ADDRESS TO CHAN BUSIN ORI CTIMAGE,ADDIN+OP1N RAISE OP AND ADDRESS IN XFR CTIMAGE,CTI SET TO HDWE AND CTIMAGE,ONES-ADDIN RESET ADDRESSIN IN IMAGE REG IF MIS GO CHECK FOR PROPER INTERFACE POLLING BOC MIFTR,HIFTR00 BRANCH IF MIS AVAILABLE CHECK TO SEE IF CONTROL UNIT END SHOULD BE ADDED TO STATUS NOTBINT1 ANDM FLAGS,CUEA MASK FOR CONTROL UNIT END A 80C DBUS,MOVEOUT BRANCH IF OFF DOACUE ORI PNDSTS,CUE SET CUE IN STATUS MOVEOU'I DQU SETLINK STO LINK1 ,SRETURND ACCEPTED STATUS RETURN STO LINK2,SRETURN1 STACK STATUS RETURN STO LINK3,PRETURNO HALTI/O RETURN NOT OPERATING CMOUP BOC CMDOUT,RSTA.DDIN WAIT COMMAND OUT R SE DOC ADROUT,PRETURNO BRANCH IF HIO BU CMOUP WAIT 0.000000000000000:anso.uuse:iaaunaacuuaczaauuuonutauat.unuaquoanlooao. ENTRY TO THIS SUBROUTINE IS FROM: CONTINIT AND CLEANI'I AND MODELINK PRIOR TO PRESENTING INITIAL STATUS TO CHANNEL. IF CHAINING IS PUT IN EFFECT THE FIRST TWO DIAGNOSTIC FLAG BY'IES WILL BE CLEARED AND BYTEO' PASSED TO ALUZ.

000038 1 3 4E 000039 0901 00003A 3701 000035 F055 0000 3C 20141 000030 F008 00003E 20in 00003F 0C00 000040 0000 000041 OC IZ 0000 2 8801 000003 R828 0000 1 4 CBFE 0000fl5 70E 000046 5741 0000147 5322 I 00 I08 62CI'J 00000) 62C7 ZITIDHA EH83 0000 18 6237 00004C 62 38 000000 SA UOUOLII 0300MB u 150 0000M UOUO IF 28 A 000050 20M 000051 29 W 000052 4560 000053 81011 00005 50 000055 (FIFE 000056 UOJGSA 0 50 000055 CQFE 00005C F50 000050 2066 00005E F506 00O0SF 2066 000060 F5 0 000061 2066 000062 F520 000063 2066 0000614 8902 000065 5122 000066 62C9 000 I M50 00068 606A 000063 CAEF 00006E 23I 3 00006F CSBF GRETURNO au GODODIAD S'IO GODODIA ANDM CHI-ZKSNS LINKQ ,STATRTN-BEGIN FLAGS,CHAIN RETURN FOR MODE CMDS SET CTL AND BURST CHI.) RETURNS MASK FOR CHAIN FLAG BOC DREG7,ALU2DIA BRANCH IF ON XOM CURCOMM,K BB MASK FOR LWR COMMAND BOC DBUS,ALU2DIA BRANCH IF SO XOM CURCOMM,X 'OB MASK FOR DIAG WRT BOC DBUS,ALU2DIA BRANCH IF SO STO SETDIAI ,0 CLEAR FLAG BYTE ONE STO SETDIA2,0 CLEAR FLAG BYTE TWO ALUZDIA XFR SETDIAI ,XOUTA MOVE FIRST FLAG BYTE TO ALUZ ORI STATIMG,SE'ISTATD SET STATD TO INDICATE SNS RESET XFR STATIMG,STAT SET TO HARDWARE AND STATIMG,ONESSETSTATD RESET STAT D IN IMAGE REG STO WORKLNDXFLAGS-ALUZBRT FETCH ALUZ SET DIAGNOSE INDEX XFR WORK2,XOUTB KICK ALU2 OFF TO FETCH BYTE XI-R LINK, IC RETURN TO INITIAL STATUS 0000000.."tt'lat'l'ttitllfltfl'tttlt STATUS S|JBROUT{NF UOOIOU'OO'IOO'UOO THI" STATUS ROUTINE HANDLES IN'I FRLOCK ING OI IN'IERFACF LINES ANI) BRANCHES TO THE APPROPRIATE SUBROUIINE DEPI NUING ON THE CHANNFI RESPONSE TO STATUS IN. THE INTERFACE WI LL ALSO BE MONITORED FOR A H IO CONDITION AND THE LINK RETURN WILl, HF EXECUTED IF HIO SHOULD OCCUR. IF THE CHANNEL ERRONEOUSLY STACKS CLEAN INITIAL STATUS A O HANG WILL OCCUR IN THE INTFERR LOOP ucuoaunatunouan:ssusn-cntancuuastun:u'utatnunanuat'tnoontousnlunauuul SRETURND BU TERMACC RETURN FOR ACCEI I'I-D STATUS SRETURNI BU TERMSTAK RETURN I-OR STACKEI) STATUS SRETURNZ BU SENSED RETURN TO SENSE ROUTINE SRETURN I BU CONTSERV RETURN FOR SERVICE SRETURNS BU CON'ISTAK RETURN TO STACK SRETURN6 BU CLEANGO RETURN FOR ACCEPTI'U S I'ATUS DEI' [NE ENTRY POINT RESE T ADORESS IN TO HDWE DEFINE ENTRY POINT HALT I/O LINK SVC OUT UP WAIT FOR DROP CMD OUT UP WAIT FOR DROP MOVE STATUS TO BUS IN MASK STATUS IN TAG UP RAISE STATUS IN MASK STATUS IN DOWN RETURN FOR STACKED CLEAN INIT S'I'S HALT I/O IIINK STACK LINK ACCEPT LINK SIATRTN EQU RSTADDIN KFR CTIMAGE,CTI STAEIRTNI EQU SVCOUTUP BOC ADROUT,HIOLINK CMOOUTUP BOC SVCOUT,SVCOUTUP BOC CMDOUT,SVCOUTUP XFR PNDSTS,CHI ORI CTIMAGE,STSIN XFR C'TIMAGE,CT I AND CTIMAGE,ONESSTSIN INTI-ERR EQU WATESUM BOC ADROUT,HIOI.INKI

BOC CMDOUT,STAKLINK BOC SVCOUT,TAKELINK BU WATESUM anazasuaouupsets:.nsautatuunutuu:tntnzunuaunacnunnnanstnnttnatuuuounto THE STAKLINK OCCURS WHFNEVER COMMAND OUT ANSWERS STATUS IN. THE STACK FLAG I S SET FOR NON-STACKABLE STATUS AND IIINKZ RETURN EXECUTED. CH'AININI} IS RESET FOR ALL STATUS FXC FII A CHANNEL END ALONE (CONTROL Q CHI) INITIAL STA IUS I anan:naaouunocscnaunuanuarnnmuuatn0:-auaunuuuuuoucanuaonto-000.0000.

STAKIII SC XIR (I IHAIJI'T,I"TI RIYSF I OP IN RAISE CUB STAKI-INK ANI) FI.AGS,I)NES'CHAIN RI-ISF'I CHAIN BIT XOM PNDST5,I)EVF.ND MASK FOR DEV END AIDNE STATUS BOC DBUS, NOS'IACK BRANCH IF SO XOH PNDSTS,DEVEND+UNI'ICHK IS STATUS READY DROP ON REW/DSE BOC DBUS,NOSTACK BRANCH IF YES TO PREVENT STACK XOH PNDSTS,BUSY MASK FOR BUSY AIDNE IN STATUS BOC DBUS,NOSTACK BRANCH IF IT IS TO PREVENT STACK XOM PNDSTS,CUE IS IT CUE AIDNE BOC )BUS,NOSTACK BR IF SO ORI FLAGS,STACK SET STACK BIT S'IOPLINK KFR LINKZ, IC XFR LINK TO 10 NOSTACK BU TERHSTKI GO RESET CHAN TAGS 00.0'.0i00.000.00.00!00.000.00.00."00..O'IIOI'OUOOOU'OOIOOI00.0000

THE IAKI'ILINK ROUTINE IS ENTERE D BY SERVICE OUT RESPONSE TO STATUS IN.

THE CHAIN, STACK, AND STATUS PENDING FLAGS ARF MANI PULATED AND CUE FOR SI-lLFCI'I-II) CHANNEL IS IS ALSO MAINTAINED HERE RESET. THE ALLOW DATA SI-IIIIRI IY ERASI'. HIAG DEPENDENT UPON CHAINING. RETURN IS VIA SKIPSUPO AND AND- FLAGS,CUEA+CUEB+INTFB*CONCON RESET CHAIN,SIAIUS PENDING AND STACK FLAGS FLAGSI ,ONES-ALIDWDSE RESET ALLOW DAT SEC ERS FLAG DID WE PRESENT CONTROL UNIT END TAKELIN'I ANDH PNDS'IS,CUE

BOC

DBUS,SERVI.INK BRANCH IF NOT A CUE WAS PRESENTED-DETERMINE THE SELECTING CHANNEL AND RESET THE CORRESPONDING CUE FLAG BOC MIFTR,MIFTROI BRANCH IF MIS AVAILABLE RSTCUEA AND FLAGS,ONESCUEA RESET CUE A FLAG XFR LINK TO IC SERVLINK XFR LINKI IC 0000 RB 00007C 000070 000071;"

000090 00009E 000091" 0000A 0000A1 0000A2 890 8 30 E01 7 2078 CAEF C9F1 6060 SAN] 6076 3110 1mm 1 2A0 SM 1 0986 8101 A150 0800 0600 4321 8600 CROP aaaZ 231 E CQDF D9 16 2090 3595 8802 WED 0828 0424 51101 8102 u360 533 ISM 1535 1536 1537 ISLAO SET CHAIN FLAG RAISE HOLD INTERFACE BIT XOM CURCOMIMX 17' IS LAST COMMAND ERASE 80C DBUS,ENABLDSE BRANCH IF SO AND FLAGSI ,ONES-ALIDWDSE RESET DSE BIT AND FLAGS,CHAIN+CUEB+CUEA+INTFB+CONCON RESET OTHER FLAGS BU TAKELINI ENABLDSE URI 1 FLAGSI ,ALLOWDSE BU SKIPIT SETCHAIN ORI FLAGS,CHAIN ORI CTIMAGE,HOLDINT SKIPIT SET THE ALLOW DSF BIT RE URN tii'ttilllltti!it!!!Ol'itttttliilllitU.It.QIIOII'...UIOII'OIQO'. H1O LINK IS ENTERED IF ADDRESS OUT IS UP OR RISE WHILE THE STATRTN ISBEING EXECUTED. RETURN I5 VIA LINK 3 WHICH IS SET UP BY THE STATRTN CALLER aooouuaunua'oauouas0n0nucotnonaat...ocaoaonauuasauuo:on:nctuoooncconoo HIOLINK XFR LINK3, IC GO HANDLE HIO HIOLINK'I XO CTIMAGE,OPIN+CUBUSY RESET OF IN RAISE CUB BOC SVCOUT,TAKEDISC BRANCH IF STATUS ACCEPTED ROC CMDOUT,STAKDISC BRANCH IF STATUS REJECTED BU HIOLINK OTHERWISE GO TO HIO NOT OPERATING I 0:noaonuatostaa:aatuauctouunuaao:tsatcan 510 ROUTINE; aaonaannnonunnaota THE START IO ROUTINE CHECKS FOR SHORT BUSY CONDITIONS. IF NONE FOUND u IT BRANCHES TO THE NO SHORT ROUTINE TO ANSWER THE SIO. no...uanuuunasuanaauuancnuooanooooosounuuuaana.:aoannaooousounoonoacuou FETCH CURRENT ADDRESS ADDRESS TO SCRATCH AREA SET HIO LINK FOR NOT OPERATING SIORTN XFR CURADDR,CBO

XFR WORKI ,CBO STO LINK3, PRETURNO XFR XOUTBIM,XOUTB TRAP ALU2 TO LOC 0 ANDM FLAGS,S'IA'IPNDG+STACK*CONCON MASK FOR PENDING OR STACKED STATUS AND CONTINGENT CONN. FLAGS BRANCH IF ALL ARE OFF BRANCH IF STACK BRANCH IF STATUS PENDING CONT CONN--CLEAR THE S'IAUS REG MOVE PEND ADDRESS TO AREG TEST FOR MATCH BRANCH IF MATCH c naus uosnom soc DREGS,NOTCONT soc DREG6,NOTCONT s10 PNDSTS,0 NOTCONT XFR PNDADDR,AR

x011 woruu ,0

50 osusmosnok'r I'lllt'ti'tl'l It'btOIODD OOOUGIOOOI.0fiiifititi...IOOOIO'I'UOUIOOUOO' THF SHOHTBUSY ROUTINE USES THE, IIPROGRAM TU MANIPULATI: BUS IN AND TAGS IN FOR A SHORT BUSY SEQUEN E. CUE IS SET IN THE STATUS. nonu'uunlntlnulonuug'uuuonuucnnuoolluanasullnnnonnasauu0tnl0lQuota-oil SHORTBSY ORI C'I'IMAGE,CUBUSY SET UP CUB BIT IN C'I'I IMAGE REG XFR C'I'IMAGE,CTI MOVE TO CHANNEL TAG IN REG ORI PNDSTS,CUE POST CUE WITH STATUS BU TERMSTAZ GO RESET CUE LATCH FOR SELECTING INTERFACE ton-uuauoatguuauucnconoannnautnunnounanso.u...nauonaoononannunoosnuooo THE NOSHORT RTN ANSWERS ADDRESS OUT AND INITIALIZES ALU 2 TO ASSEMBLE TU STATUS. VARIOUS FLAGS AND REGISTERS ARE INITIALIZED AND A CHECK IS MADE TO SEE IF A H1O HAS RECEIVED BY HARDWARE AFTER OP-IN HAS RAISED. uuunanunauouououuououolunaunutotnuonnuooano'cuaann.aunuoauaooolonnnauan NOSHORT 0!;1 CTIMAGE,OPIN MASK UP IN UP CTIMAGE,CTI RAISI' OI IN S'IO STAIIMG,0 CLEAR THE STATIMAGF REG 5T0 PNDADDR,0 CLEAR CURRENT ADDRESS REG FOR MASK XFR SELECT ADDRESS TO ALU INPUT REG MOVE ADDRESS TO PNDG ADDRESS REG STRIPADD AND HORKI ,XOF' STRIP HIGH ORDER XFR WORIU ,XOU'IA GIVE ALU 2 ADDRESS DETERMINE WHICH CHANNEL IS SELECTING AND INITIALIZE THE STAT REG, TU ADDRESS REG AND FLAGS REG.

BRANCH IF HIS AVAILABLE BOC MIFTR,MIFTR03 SETSWSEL AND RESET B FLAG ANDM XFR CURADDR,AR ORI PNDADDR 0 FLAGS,ONESINTFB E'LAGS,STATPNDG+STACK+CUEA ANY STATUS BEING HELD CHKPNDG C DBUS,SETADDR BRANCH IF NONE PENDING BOC DREG5,STRTALU2 BRANCH IF STATUS PENDING 0R1 STATIMG,SETSTATC SET SHORT INI'T SFL TO ALUZ SI-Z'IADDR STO XOUTBIILNDXSTS STRTALUZ XFR STATIMG,STAT

XFR WORKI ,TUADR XFR XOUTBIM,XOUTB ORI CTIMAGE,ADDIN XFR CURADDR,CBI

ADROUTUP BOC SETADRIN XFR WAIT FOR ADRESS OUT FALL RAISE ADDR IN ADROUT,SELOUTUP CTIMAGE,CTI

JOUDAC 0000AD 000089 0000BA 000088 0000BC 000050 OUOOBE OOOOBF 0000C0 0000(2 0000C] 000001 0000C5 00O0C6 0000CB 0000C) OOOOCA OOOOCB OOOOCC OOOOCD D901 ZDAE DC ZOAF 8810 4828 60A? CCOO DAM)

0502 B CBVF 63% J 617E 621 F 6228 622E 3BE ZBEE 3AD9 ZBAD 600 'ASSEMBLE DATA FLOW MASK WHILE SYSTEM BRINGS UP CMD OUT. illt'tiltltlit!Ottlfiililt.tit!!!O.tit"QOOIOQit"ttttitltitt'll.

SET UP FLAGS FOR TEST IS CHAIN FLAG ON? MASK TO TEST DIAG WRT BIT BRANCH IF DIAG MODE OI-F SET DIAG MODE BIT IN STAT REG SET STATS TO HDWI- GO CHECK NRZI FLAGS,CHAIN DBUS, RSTDIAG ANDM SETDIAI ,DIAWRT BOC IJBUS,CHKFTR ORI STATIMG,DIAGMODE XER STATIMG,STAT

BU CHKFTR MASEMBLE ANDM BOC SEIDUTUP BOC SEID,ADROUTUP BRANCH IE OP IN STILL PRETURND BU HIONOP GO TO HIO NOI' OPERATING RSTDIAG AND SETDIAI ,0 RESET DIAG MODE BITS CHKI-"IR HOC MIF'TR,SETSEV BRANCH IF SEVEN TK FEAT G HKNRZ ANDM RFlQTAGS,ANRZI CHECK FOR NRZI FLAG BOC DBUS,CMDWAIT BRANCH 1F NRZI BIT OFF ORI KOUTAIM,NRZMODl-. SILT XOUI'A IMAGE NR1. BIT

:uoucnasuuunconnnoauuatnununcnaoaanal-saunacaununcnanqnoanonnuuulaontou WAIT FOR AND PROCESS COMMAND OUT. DETERMINE WHETHER OPERATION CAN PROCEED. u

HALT IO NOT OPERATING FIRST COMMAND OUT WAIT II' HIT. AVA! LAHLI GO CHECK TO SEE If CONTINGENT CONNECTION FLAG CMDWAIT -l XIR CTIMAGE,CTI

ANDM I-I,AGS',STATPNDG BOC IJBUS,CMDPROC BRANCH IF MIS AVAILABLE DROP ADDRESS IN STATUS PNDING NO, GO TO CMD PROCESS CMDWAIT3 ORM CURCOMM,ZERO IS IT TEST IO BOC DBUS, PENDLINK IF YES SEND STATUS ORI PNDSTS,BUSY IF NO POST BUSY PENDLINK BU TERMSTAT GO TO RAISE STATUS IN CMDPROC BU COMDECOD GO DECODE THE CMD aununnacnnonuuuncocnnanaouuoauaunuassnnunuaoonnucononaauaunnononoooun: THE COMPARER HANDLES BUS OUT CHECKS DURING COMMAND TRANSFER. osnoncnoonunooulnnaunsauna.uannaascuuanoatnttnunntntunutnconuntnonttua CMDPARER ORI SNSSTSZ, BUSOC POST BUS OUT CHECK CMDPARO ANDM FLAGS,STATPNDG+STACK TEST FOR STATUS PENDING OR STACK BOC DBUS,CMDPAR1 BRANCH IF NO ORI PNDSTS, BUSY POST BUSY IN STATUS BU CMDWAIT GO TO STORE LINKS CMDPARI STO PNDSTS,UNI'ICHK POST A UNIT CHECK ORI FLAGS,STATPNDG POST STATUS PNDG FLAG AND FI.AG52,0NES-FORCFUC RESET FORCE UNIT CHECK FLAG STO XOUTBIM,NDXABRT-ALUZBRT LOAD ALU2 INIT ADDRESS XI-R XOUTBHLXOUTB TRAP ALUZ TO PREVENT DE RESET XFR C'IIMAGE,CTI DROP ADDRESSIN BU TERMSTAT GO TO STORE LINKS auoonucaonuounnututtt0tusnnnocoaoso QPENERS uuttunuusaatouaoonaonoto OPENERS HILL RESET THE PING HOLD LATCH IN HARDWARE IF THE COMMAND IS OTHER THAN TIO AND THE STATUS STACKED OR PENDING FLAGS ARE OFF. WHEN ALUZ COMPLETES ASSEMBLING THE DEVICE STATUS, THIS ROUTINE WILL CHECK ALU2 STATS TO DETERMINE II" THE DEVICE IS BUSY,NOT READY,OR HAS A PENDING DEV END. IF NONE OF THE-T AFOREMENTIONED ITEMS APPLY THEN THE DEVICE IS AVAILABLE AND THE COMMAND WILL BE DECODED. ALUZ STAT COMBOS' HAVE THE FOLLOWING MEANING:

' STATC=DEV END,UNT CHK( READY DROP WHEN DEV END WAS PRIMEDI STATE AND STATC=DEV END DUE TO DEV END PRIME REW -OR DSE] STATE AND STATD=DEVICE IS BUSY STATC AND STATD=DEVICE IS NOT READY 0 aaaunuuouuntnunuaatauntoastuuotuuauauanntuaonnuauonounuouttnlounlanon.

RTNCOMR BU COMREJCI RETURN TO COMMAND REJECT RTNSENS BU SENSEOK RETURN TO SENSE RTNPROT BU PROTESTI RETURN TO CHECK FILE LPROTECT RTNTUTST BU TUTESTIT RETURN TO CHECK READY RTNTUTSI BU TUTESTZ RETURN TO DO SENSE RESET BRANCH IF MIS AVAILABLE IF ALUZ FINISHED,GO LOOK FOR ERROR IF ON GO CHECK FOR PENDING DEV END BRANCH IF ON TO CHECK FOR DE, UC STS HALT IO? ALUZ STILL BUSY, GO BACK MIFTR,MIFTR02 STATD,ANYERRS STATB,CHKBUSY BOC STATC,SEEIFUC BOC ADROUT,PRETURNO BU OPENERSI OPENERS BOC OPENERS! BOC 

1. In interfacing circuits for generating an anomalous indication from a subsystem in response to a requesting signal from a controlling data processing system interconnected with said subsystem via said interfacing circuits, means chaining said subsystem to a CPU, means supplying a flag signal, means selectively setting a diagnostic mode, memory means for maintaining a status indication and a flag signal, means gating said status indication, logic means responsive to said requesting signal and another signal to generate a gating signal, the improvement including in combination: AND circuit means jointly responsive to said requesting signal and a flag signal from said subsystem to supply an enabling signal, said subsystem capable of setting said flag signal only when chained to a CPU and in a diagnostic mode of operation, encoding means responsive to said status indication or to said enabling signal to generate a code permutation representing said status indication, and said gating means being responsive to said enabling signal or to said gating signal to gate said code permutation to said CPU. 